Parallel Hardware and Parallel Software: a Reconciliation

Peter Welch

Computing Laboratory University of Kent, Canterbury, UK

Abstract

Parallel hardware is commercially marketed today at all levels of granularity – from transistors through to vector processing MPPs. Most of this is user-programmable, also at most levels of parallel granularity. A serious problem is that in order to get ‘reasonable’ (i.e. economically worthwhile) performance from these systems, proprietary software needs to be employed to exploit efficiently the underlying parallel architecture. The software models provided to the applications engineer tend to be low-level and specific to each architecture, causing difficulties for secure and verifiable design, long learning-curves and severe portability problems. Recent standardisation efforts (for message-passing interfaces and data- parallel paradigms) still appear to be too low-level and still have to prove themselves efficient. We need to have a high-level model of parallelism that is simple and architecturally neutral (so that it can be efficiently supported by current and future hardware platforms) and mathematically sound (so that it can be be made secure by a rich set of analysis and transformation tools). The applications engineer must be shielded from the parallel nature of whatever hardware is to execute the system, but must be exposed to the parallel nature of the application itself and must be able to express that freely with parallel software. Depending upon the application, the parallel software may have no direct reflection in the parallel hardware. Allowing and reconciling this divide is one of the grand challenges facing parallel hardware and software architects.

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