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$Z = XY’ + X’Y$, using only for NAND gates

I can only reduce this to five NAND gates, and can't figure out how to get four.

My work:

I took the De Morgan's Law $Z = [XY' + X'Y]'$

$= (X' + Y)(X + Y')$

$= X'X + X'Y' + XY + YY'$ ( Distributive Law )

$= X'Y' + XY$ ( Complement Law )

When I create the hardware logic diagram for this new function I receive five NAND gates.

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    Your `Z` is `X XOR Y`. See [this answer](http://electronics.stackexchange.com/a/84803) to [How to minimize the gates in implementation?](http://electronics.stackexchange.com/questions/84714/how-to-minimize-the-gates-in-implementation). – 2017-01-26

2 Answers 2

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Check the truth table of this one:

enter image description here

After discovering that we have the XOR function, you can find explanations here xor here.

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Hint:

$$(X (XY)')' = (X Y')'.$$