from Computer Organization and Design, Fourth Edition (Revised Printing)
Problems:
Do we need combinational logic, sequential logic, or a combination of the two to implement each of the following:
| a. multiplexor | e. multiplier with shifters and adders | i. carry-lookahead adder | ||
| b. comparator | f. register | j. latch | ||
| c. incrementer/decrementer | g. memory | k. general finite-state machines | ||
| d. barrel shifter | h. ALU (from the single- and multi-cycle datapaths) |
Describe the effect that a single stuck-at-0 fault (i.e., regardless of what it should be, the signal is always 0) would have for the signals shown below, in the single-cycle datapath in Figure 4.17 on page 322 of the textbook. Which instructions, if any, will not work correctly? Explain why.
Consider each of the following faults separately:
a. RegWrite = 0
b. ALUOp0 = 0
c. ALUOp1 = 0
d. Branch = 0
e. MemRead = 0
f. MemWrite = 0
We wish to add the instruction jr to the single-cycle
datapath described in Chapter 4 of the textbook.
Add any necessary datapaths and control signals to the single-cycle
datapath of Figure 4.17 on page 322 and show the necessary additions to
Figure 4.18 on page 323.
This question is similar to the previous one except that we wish to add a
variant of the lw (load word) instruction, which increments
the index register after loading the word from memory.
This instruction (named l_inc) corresponds to the following
two instructions:
lw $rt, L($rs) addi $rs, $rs, 4
Problem 4.2.1 from the textbook
Problem 4.2.2 from the textbook
Problem 4.6.4 from the textbook
Problem 4.6.5 from the textbook