Problem Set 1

from Computer Organization and Design, Fourth Edition (Revised Printing)

Problems:

Problem 1.1 from the textbook
Convert the following decimal values into 32-bit two's complement binary numbers:
- 4096
- -2047
- -2,000,000
What decimal numbers do the following 32-bit binary numbers represent, assuming a 32-bit two's complement representation:
- 1111 1111 1111 1111 1111 1111 0000 0110
- 1111 1111 1111 1111 1111 1111 1110 1111
- 0111 1111 1111 1111 1111 1111 1110 1111
Find the shortest sequence of MIPS instructions to calculate the absolute value of an integer held in a register. Convert this instruction (accepted as a pseudo-instruction by the assembler):
```
abs  $t2, $t3
```
This instruction copies $t3 into $t2 if register $t3 contains a non-negative value, and copies the two's complement of $t3 into $t2 if $t3 contains a negative number. (Hint: this can be done with three instructions.)
If A is a 32-bit address, typically an instruction sequence such as
```
lui  $t0, A_upper
ori  $t0, $tg0, A_lower
lw   $s0, 0($t0)
```
(where A_upper is the upper 16 bits of the address A, and A_lower is the lower 16 bits of that address) can be used to loasd the word at A into a register (in this case, $s0). Consider the following alternative, which is more efficient:
```
lui  $t0, A_upper_adjusted
lw   $s0, A_lower($t0)
```
Describe how A_upper is adjusted to allow this simpler code to work (Hint: A_upper must be adjusted because A_lower, which is the offset in the memory address calculation, will be sign-extended.)
Find the shortest sequence of MIPS instructions to determine if there is a carry out from the addition of two registers (e.g., registers $t3 and $t4). Place a 0 or 1 in register $t2 if the carry out is 0 or 1, respectively. (Hint: it can be done in two instructions.)
Suppose that all of the conditional branch instructions except beq and bne were removed from the MIPS instruction set along with slt and all of its variants (slti, etc.). Show how the instruction
```
slt  $t0, $s0, $t1
```
could be performed using the modified instruction set in which slt is not available. (Hint: it requires more than two instructions.)
Recall that a sequence of bits has no inherent meaning. Given the bit pattern
```
1010 1101 0001 0000 0000 0000 0000 0010
```
what does it represent, assuming that it is:
- A) a two's complement integer?
- B) an unsigned integer?
- C) a single-precision floating-point number?
- D) a MIPS instruction?
You may find Figures 3.19 (page 261) and B.10.2 (page B-50) useful.
Repeat the previous exercise for this bit pattern:
```
0010 0100 1001 0010 0100 1001 0010 0100
```
The internal representation of floating-point numbers in the Intel IA32 architecture is 80 bits wide. This contains a 16-bit exponent. However, it also advertises a 64-bit significand. How is this possible?