Homework 3

1. Book A.1

2. Book A.10

3. Book A.18 b,c,d
   Answer to part a

4. Several researchers have suggested that adding a register-memory addressing mode to a load-store machine might be useful. The idea is to replace sequences of:

   
   LW	R1, 0(R5)
   ADD	R2, R2, R1
   

   by

   
   ADD	R2, 0(R5)
   

   Assume the new instruction will cause the clock cycle to increase by 5%. Use the instruction frequencies for the gcc benchmark on the load-store machine from figure A.27. The new instruction affects only the clock cycle and not the CPI.
   1. What percentage of the loads must be eliminated for the machine with the new instruction to have at least the same performance?
   2. Show a situation in a multiple instruction sequence where a load of R1 followed immediately by the use of R1 (with some type of opcode) could not be replaced by a single instruction of the form proposed assuming that the same opcode exists.

5. Consider adding a new indexed addressing mode to MIPS. The addressing mode adds two registers and an 11-bit signed offset to get the effective address.

   Our compiler will be changes so that code sequence of the form:

   
   ADD	R1, R1, R2
   LW	R4, 100(R1)
   

   will be replaced with a load using the new addressing mode. Use the overall average instruction frequencies from figure A.27 in evaluating this addition.

   1. Assuming that the addressing mode can be used for 10% of the displacement loads and stores (accounting for both the frequency of this type of address calculation and the shorter offset). What is the ratio of instruction count on the enhanced MIPS compared to the original MIPS?
   2. If the new addressing mode lengthens the clock cycle by 5% which machine will be faster and by how much?