520/720 DLX Instruction Set

Last updated 2003/04/27

Update history:

2003/04/27: the ANDI, ORI, XORI, SLLI, SRLI, SRAI have their immediate value zero-extended, not sign-extended
2003/04/18: JR and JALR are I-type, not R-type
2002/02/14: initial version produced by Prof. Carithers

1. Introduction

This document is a summary of the DLX instruction set, as presented in Computer Architecture: A Quantitative Approach, second edition.

2. Addressing Modes

Here is a summary of the DLX addressing modes as described in the text:

Name Syntax Description
Immediate #i The value i is the contents of the 16-bit immediate operand field. Can only be used with I-type instructions. Note that the value may be interpreted as a signed or unsigned value, depending upon the instruction.
Register Rn Register n.
Displacement d(Rn) Memory operand, located at the address d+Rn. Can only be used with I-type instructions; the displacement is held in the imm field, and must be sign-extended.

3. Instructions

The DLX instruction set contains the following operations:

Miscellaneous:

Syntax Format Description
TRAP #n J-type Generate a TRAP interrupt; n is the trap number, represented in the 26-bit offset field.


Load:

Syntax Format Description
Lx Rn,src I-type Load into register n from src; x indicates the type of data being loaded (B, H, W); B and H sign-extend the data to 32 bits prior to loading the register.
LxU Rn,src I-type Load Unsigned; like Lx, but for types B and H the data are zero-extended.
LHI Rn,#imm I-type Load High Immediate; register n is loaded from the immediate operand field, which is shifted left by 16 bits before being loaded.
Sx Rn,dst I-type Store from register n into dst; x indicates the type of data being stored: B, H, W


Set:

Syntax Format Description
Sc Rd,Rs1,Rs2 R-type Set; c is a condition specifier (EQ, NE, LT, LE, GE, GT); contents of registers s1 and s2 are compared; register d is set to 1 if the condition is true, otherwise it is set to 0.
ScU Rd,Rs1,Rs2 R-type Set Unsigned; like Sc, but the comparison is done assuming the operads contain unsigned values.
ScI Rd,Rs1,#imm I-type Set Immediate; like Sc, but compares register s1 to the sign-extended imm field.
ScUI Rd,Rs1,#imm I-type Set Immediate Unsigned; like ScI, but imm is zero-extended, and the comparison is unsigned.


Arithmetic/Logic:

Syntax Format Description
TRAP R-type Arithmetic Trap; like the regular TRAP, but doesn't have a trap number.
NOP R-type No-op; does nothing, but does it gracefully.
ADD Rd,Rs1,Rs2 R-type Add; the contents of registers s1 and s2 are added, and the result is placed in register d.
ADDU Rd,Rs1,Rs2 R-type Like ADD, but assumes unsigned values.
ADDI Rd,Rs1,#imm I-type Like ADD, but the second operand is the sign-extended imm field.
ADDUI Rd,Rs1,#imm I-type Like ADDU, but the second operand is the zero-extended imm field.
SUB Rd,Rs1,Rs2 R-type Subtract; the contents of register s2 is subtracted from the contents of register s1, and the result is placed in register d.
SUBU Rd,Rs1,Rs2 R-type Like SUB, but assumes unsigned values.
SUBI Rd,Rs1,#imm I-type Like SUB, but the second operand is the sign-extended imm field.
SUBUI Rd,Rs1,#imm I-type Like SUBU, but the second operand is the zero-extended imm field.
AND Rd,Rs1,Rs2 R-type Like ADD, but performs a logical AND operation.
ANDI Rd,Rs1,#imm I-type Like AND, but the second operand is the zero-extended imm field.
OR Rd,Rs1,Rs2 R-type Like AND, but performs a logical OR operation.
ORI Rd,Rs1,#imm I-type Like OR, but the second operand is the zero-extended imm field.
XOR Rd,Rs1,Rs2 R-type Like AND, but performs a logical XOR operation.
XORI Rd,Rs1,#imm I-type Like XOR, but the second operand is the zero-extended imm field.
SLL Rd,Rs1,Rs2 R-type Shift Left Logical; the contents of register s1 are shifted left (and zero-filled) by the number found in register s2, and the results are placed in register d. zeroes
SLLI Rd,Rs1,#imm I-type Like SLL, but the shift count is the zero-extended imm field.
SRL Rd,Rs1,Rs2 R-type Shift Right Logical; like SLL, but performs a right logical shift.
SRLI Rd,Rs1,#imm I-type Like SRL, but the shift count is the zero-extended imm field.
SRA Rd,Rs1,Rs2 R-type Shift right Arithmetic; like SRL, but performs a right arithmetic shift, filling with copies of the original sign bit.
SRAI Rd,Rs1,#imm I-type Like SRA, but the shift count is the zero-extended imm field.


Transfer:

Syntax Format Description
J dst J-type Jump; the 26-bit offset field of the instruction is sign-extended to 32 bits and added to the PC.
JR Rs1 I-type Jump Register; like J, but transfers to the address found in register s1.
JAL dst J-type Jump And Link; like J, but copies the PC into R31 before the transfer.
JALR Rs1 I-type Jump And Link Register; like JAL, but transfers to the address found in register s1.
BEQZ Rs1,dst I-type Branch on Equal to Zero; if the contents of register s1 equals zero, transfer to the destination, which is calculated by adding the sign-extended imm field contents to the PC.
BNEZ Rs1,dst I-type Branch on Not Equal to Zero; if the contents of register s1 does not equal zero, transfer to the destination, which is calculated by adding the sign-extended imm field contents to the PC.


Floating-Point ALU:

These are actually integer instructions, but they are part of the floating-point set because the original DLX design assumed that they would be implemented by the floating-point coprocessor due to their execution times.

Syntax Format Description
MUL Rd,Rs1,Rs2 R-type Multiply; multiples the contents of registers s1 and s2, and places the product in register d.
MULU Rd,Rs1,Rs2 R-type Like MUL, but assumes unsigned values.
DIV Rd,Rs1,Rs2 R-type Divide; divides the contents of register s1 by the contents of register s2, and places the quotient in register d.
DIVU Rd,Rs1,Rs2 R-type Like DIV, but assumes unsigned values.
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