Computer Organization -- Final Exam Topics

As this is a comprehensive exam, you may also wish to review the Exam 1 and Exam 2 topic lists.

need to support all necessary operations
- arithmetic
- logical
- shift/rotate
- sign extension
design philosophy #1
- for simplicity, build 32 one-bit ALUs, then figure out how to connect them
design philosophy #2
- build separate hardware blocks for each task
- perform all possible operations in parallel
- use a mux to choose which operation is actually desired
important concept: use multiplexors whenever we need to select between alternative inputs or results
simple one-bit ALU
- N different simple
- use Nx1 mux to select desired operation
- operations:
  - AND, OR, XOR, etc. with individual gates
  - addition with full adder
  - subtraction with full adder and two's complement trick
tailor ALU to needs of ISA
- e.g., for MIPS, need set-on-less-than, zero
important details
- ALU is combinational - always active
- speed depends on size
  - more complex ALU is larger, therefore slower
  - can improve speed with carry-lookahead adders
communicate with buses
- method 1: use multiplexors to generate bus lines
- method 2: use tri-state devices

general concepts
- break up task of ``executing an instruction'' into stages
- connect the stages to create the entire datapath
- smaller stages are easier to design than entire ``execution unit''
- easy to optimize/change one stage without touching the others
typical stages
- instruction fetch - all
- instruction decode / register fetch - all
- execution - varies according to need of instruction
- memory access - load and store only
- register write - ALU and load only
describe stages with RTL
standard components
- register file
- PC
- ``add four'' unit
- sign-extender
- instruction memory
- data memory
- ALU
- tie components together with multiplexors
implementation choices
- single-cycle: perform all tasks in a single clock cycle
- multi-cycle: use a clock cycle for each stage
control signals
- needed to direct operation of datapath components
- generate them combinationally based on opcode, function code

control signals depend upon
- instruction being executed
- which step is being performed
use a finite state machine to design control
- set of states
- ``next state'' function
- output function
generating states
- sequence generator
  - a.k.a. counter
  - feed output into a decoder to generate state signals
  - combinational circuitry uses state signals to generate control signals
  - problem: may have many unused states
implementing control functions
microprogrammed control units
- background and basic concepts
  - control word
  - microinstruction, microprogram
  - static vs. dynamic microprogram
- basic MCU configuration
- sequencing
  - sequential execution
  - branching: conditional, unconditional, call/return
- microinstruction formats
  - vertical vs. horizontal vs. hybrid
  - control fields
  - grouping of micro-ops into control fields
- microinstruction source code
- pros and cons of microprogramming